Field of the Invention
The present invention relates to a semiconductor device and a semiconductor module having the semiconductor device and, in particular, relates to a semiconductor device having an impedance calibration function to a data output buffer and a semiconductor module having the semiconductor device.
Description of Related Art
Some semiconductor devices that perform high-speed data transfer, such as DRAM (Dynamic Random Access Memory), include a calibration circuit for adjusting an impedance of a data output buffer. The calibration circuit includes a calibration terminal and a replica buffer connected thereto. The replica buffer is a circuit having substantially the same circuit structure as that of the data output buffer. To the calibration terminal, an external resistance having a target impedance of the data output buffer is connected. Calibration is performed by adjusting impedance of the replica buffer so as to correspond to the impedance of the external resistance, and reflecting the adjusted impedance on the data output buffer (refer to Japanese Patent Application Laid-Open No. 2010-21994).
According to a calibration circuit described in the Japanese Patent Application Laid-Open No. 2010-21994, a level of a reference potential to be compared with a potential of a calibration terminal is set to one half (0.5 VDD) of a power supply potential (VDD). Depending on specifications, however, the reference potential may be set to the level offset from one half of the power supply potential, which makes it difficult to perform precise calibration operation at all times.